1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and more specifically, to a method of manufacturing a semiconductor device with low-k spacers composed of multilayer and the semiconductor devices incorporating such low-k spacers.
2. Description of the Prior Art
The manufacture of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of such integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, whether an NFET or a PFET device, is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, a gate insulating layer and a gate electrode positioned above the gate insulating layer over the channel region. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
For many early device technology generations, the gate structures of most transistor elements has been comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulating layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. Gate structures that include a so-called high-k dielectric gate insulating layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/poly-silicon gate structure configurations. One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement metal gate” (RMG) technique.
In a conventional RMG process, spacers at both sides of the dummy poly-silicon gate are vulnerable to the etching process for removing the sacrificial gate insulating layer after the poly-silicon gate electrode is removed. The consumption of the spacers may cause CD (critical dimension) bias on the resulting metal gate structure. Additionally, with the reduction of the width of the spacers due to the consumption, the parasitic capacitance of the semiconductor device would be increased and affects its electrical performance. Therefore, it is necessary for those skilled in the art to develop an effective structure or method to solve this issue.